The present invention relates to semiconductor IGFET devices.
An Insulated-Gate Field-Effect Transistor, or IGFET, is a device of very major importance in the semiconductor IC industry. A Metal-Oxide-Silicon Field-Effect Transistor, or MOSFET, is a sub-class of IGFET devices. An IGFET is a four terminal device comprising of a source, drain, gate and body nodes; though the body node only allows very limited access to the device. MOSFETs are widely used in the sub micron semiconductor processing technologies to manufacture Ultra Large Scale Integrated Circuits. Ability to form Silicon-oxide interfaces with very low interface states, quality gate oxides with low thickness, reductions in system voltage and reductions in lateral geometries by lithography improvements have all contributed to the popularity of these transistors. Today MOSFETs are used to build ASICs, Memory, FPGA, Gate Array, Graphics, Micro Processors, and a wide variety of semiconductor IC products.
IGFET differ from a Bipolar Transistor in the power level and power amplification available in the device. Bipolar transistor is a three terminal device with a base, an emitter and a collector node. Compared to the base control terminal of a Bipolar transistor, the gate control terminal of IGFET consumes essentially no power. While the Bipolar can deliver more output power, the gain (defined by the ratio of output current to control current) is infinite for IGFET compared to about 500 for a good Bipolar transistor. This high gain coupled with complementary MOSFET design methodology facilitates low stand-by power in ICs that have over 10 Million transistors. Bipolar is used to build many Analog and Linear ICs such as voltage regulators, power amplifiers, rectifiers, battery regulators, D to A Converters and A to D Converters due to the high output power available. Sub-micron geometry MOSFETs with high current drives are now increasingly used for similar applications.
IGFET differs from a JFET, also a three terminal device, in the construction of the transistor. In the IGFET the gate is insulated above the transistor body, while in the JFET the gate is formed as a reverse biased junction above the conducting channel. The reverse bias control gate junction consumes a low level of power due to carrier recombination inside the depleted region. The JFET power amplification is better than a Bipolar, but lower than an IGFET. A significant difference between IGFET and JFET occurs in the method of channel conduction. This will be discussed in detail next.
The MOSFET operates by conducting current between its drain and source through a conducting inversion layer created by the presence of a gate voltage. FIG. 1 shows a cross section of a MOSFET device, and is described herein with reference to an NMOSFET device. In FIG. 1, an NMOS transistor body 100 is P− doped, isolating an N+ doped source region 113 and an N+ doped drain region 114. The source is connected to a first voltage 103, which may be the ground supply VS. The drain is connected to a second voltage 104, which may be a switching voltage node for the device. The body region between source and drain under the gate 112 is also doped P type same as substrate. The result is the formation of two N+/P− back-to-back reverse-biased diodes. When the voltage 102 at gate 112 is zero, or below a threshold voltage VTN, the N+/P− back-to-back reverse-biased diodes do not conduct and the transistor is off. The surface under gate 112 consists of hole carriers. In the embodiment of FIG. 1, the gate 112 includes a salicided region shown shaded, and the source and drain salicidation is not shown. When the gate voltage is greater than a threshold voltage (VTN), an inversion 110 occurs under gate 112. This inversion layer, called a conducting channel, completes an electron carrier path between the source 103 and drain 104 regions. For the MOSFET in FIG. 1, the terminology inversion layer and conducting channel is used interchangeably, and is shown by 110. This conducting channel facilitates current flow between source 113 and drain 114 regions. Hole carrier depletion occurs adjacent to the body region 100 under the inversion layer 110 and adjacent to source 113 and drain 114 regions. This is shown shaded in FIG. 1. This charge is due to the reversed bias electric fields from the gate, source and drain voltages. The component of this depleted charge from the gate voltage determines the magnitude of the VTN. Trapped oxide charge and Silicon defects affect the VTN transistor parameter. The more positive the voltage is at the gate, the stronger is the inversion layer charge and hence the channel conduction. At all levels, the substrate 100 potential is kept at the lowest voltage level. In most applications, the substrate and source are held at VS. For special applications, the NMOS body can be pumped to a negative voltage.
A PMOS device is analogous to an NMOS device, with the device operational polarity and doping types reversed. A PMOS is on when the gate is in the voltage range from system ground VS to a threshold difference (VD−VTP), and off when the gate is in the voltage range (VD−VTP) to system power voltage VD. Channel conduction is between P+ doped source and P+ doped drain, via a surface inversion P− layer. The body region originally doped N− gets depleted by the gate potential. The body region for a PMOS is termed Nwell and is constructed on a P type substrate wafer as an isolated island. The Nwell is biased to the highest PMOS device potential, and in most applications the source and Nwell are held at VD. For special applications, the PMOS body can be pumped to a voltage higher than the power supply voltage.
In a MOSFET device, there is a body region 100 under the gate. In fact, a conducting channel is not formed until the surface is in inversion with a build up of minority carriers. The gate depletes the body region near the surface to create this inversion layer at the surface. The depletion width reaches a maximum depth at the onset of inversion, and stays constant at higher gate biases. As the body extends well into the bottom surface of the substrate, the gate modulation has little impact on the resistance of the body region between the source and drain regions. A special case of a MOSFET is a depletion device. In the NMOS depletion device, an N− implanted channel is formed under the gate on the device body surface between N+ source and N+ drain regions. This depletion device has a negative threshold voltage, and a negative gate voltage is needed to turn the device off. The channel is modulated by two terminals: the gate above the oxide, and the body below the channel. The body below has a significant impact on the channel resistance, and in some depletion devices a negative body bias is needed to turn the depletion device off completely.
As discussed in U.S. Pat. No. 5,537,078, conventional JFET transistors are of two main types: P-channel (PJFET) and N-channel (NJFET). FIG. 2 shows a cross section of a JFET device. The description that follows is for an NJFET device. In FIG. 2, a semiconductor channel 206 which has been doped N− is positioned between two N+ diffusions 213 and 214. These diffusion nodes are connected to two terminals 203 and 204 respectively. The terminal supplying the majority carrier to the channel (which is the lowest potential) is designated the source (S) while the other terminal is designated the drain (D). Across the N− channel 206 there are two gates which are referred to as the top gate 212 and the bottom gate 222. Top gate is connected to terminal 202, and the bottom gate is connected to terminal 232. In some embodiments, the two gate terminals 202 and 232 may be common. Each gate is doped with P+ type dopant to create two back to back P+/N− diodes perpendicular to the channel. When drain and source voltages are different, the drain to source current passes entirely through the conducting N− channel 206. This current increases with higher voltage drop between the terminals, reaching a saturation value at high biases. At saturation, the depletion regions meet at a pinch-off point 230 near the drain edge as shown in FIG. 2. The gates are biased to keep the gate to channel P+/N− junctions reversed biased. The reversed biased voltage creates depletion regions 210 and 220 that penetrate into the channel reducing the channel height available for current flow. The gate voltages also control the flow of current between the source and drain by modulating the channel height. When the gate reverse bias is sufficiently large, the entire channel is pinched-off causing no current flow between drain and source. In on and off states, there is no current flow through the gate terminal of a JFET due to reverse bias junction voltages, except for junction leakage current. For the device in FIG. 2 a negative gate voltage (lower than VS) creates the channel off condition. Such a negative gate voltage increases the operating voltage of this process, a draw back for JFET scheme.
A PJFET device is analogous to an NJFET device, with the device operational polarity and doping types reversed. A PJFET is on when the gate is at VD, and off when the gate is more positive than VD further increasing the voltage level of the process. Channel conduction is between P+ doped source and drain regions via a P− doped channel sandwiched between two N+ doped gate regions. For source and drain terminals at voltages in the range from VS to VD, operating range of NJFET gate is less than VS to VS, while the operating range for PJFET gate is VD to more than VD.
Compared to the non-conducting body 100 of MOSFET on FIG. 1, the JFET has a conducting channel 206 between source and drain. Due to non-overlapping gate voltages and the high voltage range thus needed, a complementary JFET process is impractical to realize. Hence there is no low cost process that provides CJFET devices analogous to CMOS devices. Compared to the MOSFET in FIG. 1, a JFET conducting channel is formed inside the body of the switching device. This channel current is not affected by trapped oxide charges near the gate, a draw back with MOSFETs. Compared to MOSFETs, JFETs also have poorer switching characteristics due to higher depleted charge stored in the channel and the transient times required to store and remove this depletion charge. Reverse biased junctions hurt JFET device ease of use and popularity in modern day ICs.
A special MOSFET device constructed in Silicon-on-Insulator (SOI) is shown in FIG. 3. This three terminal device is constructed as either an NMOSFET or a PMOSFET. The difference in FIG. 1 and FIG. 3 is in the thickness of the body region 306 of the device, and in its body isolation. In the SOI device, the regions 313, 306 and 314 are constructed on a thin film semiconductor material. The substrate 300 is isolated from the device region by insulator 307, hence there is no fourth terminal to this device. This isolation helps with lower junction capacitance and no body effect for SOI MOSFET. Source 313, drain 314, gate 312, spacer 320, and salicided regions 322 and 325 are all similar to the standard MOSFET in FIG. 1. Two conditions differ in SOI MOSFET when the device in on. In PD SOI, the body 306 is only partially depleted (PD) when the body is thicker than a maximum depletion width. Then a neutral floating body exists inside region 306 causing deleterious effects on device performance. For thinner FD SOI devices the body is fully depleted (FD) and a neutral body region does not occur. These tend to show short channel effects from the drain and source reverse biased depletions into body region.
Analogous to standard MOSFET, SOI MOSFET also has a non-conducting body under the gate 312. The channel 310 is only formed by inverting the surface. The body 306 is fully isolated with no access points. The gate modulation of the body has no influence to access ports. Unlike the body, the conducting channel can be accessed via source and drain nodes. There is no analogous device to depletion MOSFET in SOI. This is due to the floating body in an SOI and the inability to control body voltage. Depletion device behavior strongly depends on the body voltage control.